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| version 2.5.4 proprietary and confidential longest match engine KE5BLME064 ver. 2.5.4 kawasaki lsi u.s.a., inc.
version 2.5.4 proprietary and confidential table of contents 1. features ................................................................................................................... ............................. 1 2. block diagram .............................................................................................................. ........................ 2 3. pin assignment and description............................................................................................. ........... 3 3.1. pin assignment: diagram .................................................................................................. ............. 3 3.2. pin assignment: list.................................................................................................... ................. 4 3.3. pin description.......................................................................................................... ...................... 6 4. functional descriptions .................................................................................................... .................. 9 4.1. overview ................................................................................................................. ........................ 9 4.2. reset.................................................................................................................... ........................... 9 4.3. initialization ........................................................................................................... ........................ 10 4.4. data insertion........................................................................................................... ..................... 10 4.5. search................................................................................................................... ........................ 11 4.6. data deletion......14 4.7. data insertion/deletion rate........14 4.8. search via cpu port...................................................................................................... ............... 14 4.9. interruption............................................................................................................. ....................... 15 4.10. typical operational flow................................................................................................. .............. 17 4.11. cascade connection......17 5. sram....................................................................................................................... ............................ 20 5.1. sram specification ....................................................................................................... ............... 22 5.2. connecting to sram ....................................................................................................... ............. 22 6. register ................................................................................................................... ............................ 23 6.1. register map............................................................................................................. .................... 23 6.2. register description ..................................................................................................... ................ 23 7. command description............................................................................................................ ........... 27 8. package outline ............................................................................................................ ..................... 33 9. electrical characteristics ................................................................................................. ................. 34 9.1. absolute maximum rating.................................................................................................. .......... 34 9.2. operating conditions ..................................................................................................... ............... 34 9.3. dc characteristics ....................................................................................................... ................. 34 9.4. ac characteristics ....................................................................................................... ................. 35 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 1 1. features the KE5BLME064 provides the best solution to a high-speed route search with the following functions: ? 64k route entries the device can store 65,528-route prefixes each entry has 40-bit width ? clock maximum clock frequency: 66 mhz ? longest match search capability ? exact match search capability ? search throughput 6.7 mpps (packet per sec. at 66mhz clock) (10 clocks) ? search latency 270 ns (hit flag; match length output) (18 clocks) 555 ns (associative data output) (37 clocks) ? data insertion/deletion 534 entries/sec typical (during search operation) (66mhz) 400k entries/sec maximum (during initialization operation) (66mhz) ? triple-port architecture cpu port: 16 bit input port: 40 bit output port: 18 bit ? embedded external sram control 3pcs of 2mbits flow through type synchronous burst sram ? cascade connection to increase density ? interface lvttl ? voltage single 3.3v 0.3v supply ? package 416 bga ( bga352+tb64, tb:thermal ball ) ? cmos technology kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 2 2. block diagram fig. 2.1 block diagram output port add[3:0] hon cpu port sram1,2,3 port mbwd3n mbwc3n mbwb3n mbwa3n mbwe3n mdat3[31:0] mcs3n moe3n madd3[15:0] mbwd1n mbwc1n mbwb1n mbwa1n mbwe1n mdat1[31:0] mcs1n moe1n madd1[15:0] mbwd2n mbwc2n mbwb2n mbwa2n mbwe2n mdat2[31:0] mcs2n moe2n madd2[15:0] dat[15:0] cen rwn irqn fln amfln ccmpn rstn input port clk srchn inp[39:0] registers control logic s r a m control ins/del queue search table odonen out[17:0] oen mdonen mle[5:0] mloen kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 3 pin assignment and description 3.1 pin assignment: diagram fig. 3.1 pin assignment bottom view index top view 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 a b c d e f g h j k l m n p r t u v w y 26 25 24 23 22 21 a f a e a d a c a b a a kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 4 3.2 pin assignment: list no. pin name i/o no. pin name i/o no. pin name i/o no. pin name i/o a1 gnd - b19 mloen in d11 dat<15> io h23 gnd - a2 inp<28> in b20 out<17> out d12 gnd - h24 madd3<10> out a3 inp<21> in b21 out<16> out d13 dat<8> io h25 madd3<9> out a4 inp<16> in b22 out<13> out d14 dat<4> io h26 madd3<8> out a5 inp<12> in b23 out<10> out d15 vdd - j1 gnd - a6 inp<9> in b24 out<6> out d16 rstn in j2 madd1<1> out a7 inp<5> in b25 gnd - d17 gnd - j3 madd1<2> out a8 inp<2> in b26 gnd - d18 mle<4> out j4 gnd - a9 irqn out c1 inp<35> in d19 vdd - j23 vdd - a10 ccmpn out c2 inp<29> in d20 gnd - j24 madd3<12> out a11 dat<12> io c3 inp<23> in d21 gnd - j25 madd3<11> out a12 dat<9> io c4 inp<18> in d22 gnd - j26 vdd - a13 dat<5> io c5 inp<14> in d23 gnd - k1 madd1<3> out a14 dat<1> io c6 inp<11> in d24 out<8> out k2 madd1<4> out a15 dat<0> io c7 inp<7> in d25 out<4> out k3 madd1<5> out a16 add<0> in c8 inp<4> in d26 out<1> out k4 gnd - a17 mle<5> out c9 inp<0> in e1 inp<37> in k23 vdd - a18 mle<1> out c10 amfln out e2 inp<31> in k24 madd3<15> out a19 mle<0> out c11 dat<14> io e3 inp<25> in k25 madd3<14> out a20 oen in c12 dat<11> io e4 inp<19> in k26 madd3<13> out a21 out<15> out c13 dat<7> io e23 madd3<2> out l1 madd1<6> out a22 out<12> out c14 dat<3> io e24 madd3<1> out l2 madd1<7> out a23 out<9> out c15 add<3> in e25 madd3<0> out l3 madd1<8> out a24 out<5> out c16 add<2> in e26 odonen out l4 madd1<9> out a25 out<2> out c17 rwn in f1 inp<38> in l23 gnd - a26 vdd - c18 mle<3> out f2 inp<32> in l24 mdat3<2> io b1 inp<34> in c19 mdonen out f3 inp<26> in l25 mdat3<1> io b2 vdd - c20 hon out f4 gnd - l26 mdat3<0> io b3 inp<22> in c21 vdd - f23 vdd - m1 madd1<10> out b4 inp<17> in c22 out<14> out f24 madd3<5> out m2 madd1<11> out b5 inp<13> in c23 out<11> out f25 madd3<4> out m3 madd1<12> out b6 inp<10> in c24 out<7> out f26 madd3<3> out m4 vdd - b7 inp<6> in c25 out<3> out g1 inp<39> in m23 gnd - b8 inp<3> in c26 out<0> out g2 inp<33> in m24 mdat3<5> io b9 srchn in d1 inp<36> in g3 inp<27> in m25 mdat3<4> io b10 fln out d2 inp<30> in g4 inp<20> in m26 mdat3<3> io b11 dat<13> io d3 inp<24> in g23 gnd - n1 madd1<13> out b12 dat<10> io d4 vdd - g24 gnd - n2 madd1<14> out b13 dat<6> io d5 inp<15> in g25 madd3<7> out n3 madd1<15> out b14 dat<2> io d6 vdd - g26 madd3<6> out n4 gnd - b15 gnd - d7 inp<8> in h1 gnd - n23 mdat3<9> io b16 add<1> in d8 gnd - h2 open - n24 mdat3<8> io b17 cen in d9 inp<1> in h3 madd1<0> out n25 mdat3<7> io b18 mle<2> out d10 vdd - h4 vdd - n26 mdat3<6> io kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 5 no. pin name i/o no. pin name i/o no. pin name i/o no. pin name i/o p1 mbwe1n out w23 vdd - ac17 vdd - ae9 mdat2<9> io p2 mcs1n out w24 mdat3<17> io ac18 vdd - ae10 mdat2<12> io p3 moe1n out w25 mdat3<16> io ac19 gnd - ae11 mdat2<15> io p4 gnd - w26 mdat3<15> io ac20 gnd - ae12 mdat2<19> io p23 gnd - y1 mdat1<10> io ac21 vdd - ae13 mdat2<22> io p24 gnd - y2 mdat1<11> io ac22 vdd - ae14 mdat2<24> io p25 mbwd3n out y3 gnd - ac23 gnd - ae15 mdat2<28> io p26 gnd - y4 gnd - ac24 mdat3<27> io ae16 mdat2<31> io r1 mbwc1n out y23 mdat3<20> io ac25 mdat3<26> io ae17 mbwb2n out r2 mbwd1n out y24 mdat3<19> io ac26 mdat3<25> io ae18 mbwd2n out r3 gnd - y25 gnd - ad1 mdat1<20> io ae19 madd2<14> out r4 gnd - y26 mdat3<18> io ad2 mdat1<21> io ae20 madd2<13> out r23 vdd - aa1 mdat1<12> io ad3 mdat1<22> io ae21 madd2<10> out r24 mbwc3n out aa2 mdat1<13> io ad4 mdat1<23> io ae22 madd2<7> out r25 moe3n out aa3 mdat1<14> io ad5 mdat1<24> io ae23 madd2<4> out r26 clk in aa4 vdd - ad6 mdat2<1> io ae24 madd2<2> out t1 mbwa1n out aa23 gnd - ad7 mdat2<4> io ae25 mdat3<31> io t2 mbwb1n out aa24 mdat3<22> io ad8 mdat2<7> io ae26 mdat3<30> io t3 mdat1<0> io aa25 mdat3<21> io ad9 gnd - af1 vdd - t4 mdat1<1> io aa26 vdd - ad10 mdat2<13> io af2 mdat1<29> io t23 mcs3n out ab1 mdat1<15> io ad11 mdat2<16> io af3 gnd - t24 mbwa3n out ab2 mdat1<16> io ad12 mdat2<20> io af4 mdat1<30> io t25 mbwb3n out ab3 mdat1<17> io ad13 mdat2<23> io af5 mdat1<31> io t26 gnd - ab4 vdd - ad14 mdat2<25> io af6 vdd - u1 mdat1<2> io ab23 gnd - ad15 mdat2<29> io af7 mdat2<2> io u2 mdat1<3> io ab24 gnd - ad16 moe2n out af8 mdat2<5> io u3 mdat1<4> io ab25 mdat3<24> io ad17 mcs2n out af9 mdat2<8> io u4 vdd - ab26 mdat3<23> io ad18 mbwe2n out af10 mdat2<11> io u23 gnd - ac1 mdat1<18> io ad19 madd2<15> out af11 mdat2<14> io u24 mdat3<11> io ac2 gnd - ad20 gnd - af12 mdat2<18> io u25 mdat3<10> io ac3 mdat1<19> io ad21 madd2<11> out af13 mdat2<21> io u26 mbwe3n out ac4 gnd - ad22 madd2<8> out af14 gnd - v1 gnd - ac5 gnd - ad23 madd2<5> out af15 mdat2<27> io v2 mdat1<5> io ac6 gnd - ad24 gnd - af16 mdat2<30> io v3 mdat1<6> io ac7 gnd - ad25 mdat3<29> io af17 mbwa2n out v4 vdd - ac8 vdd - ad26 mdat3<28> io af18 mbwc2n out v23 mdat3<14> io ac9 mdat2<10> io ae1 mdat1<25> io af19 gnd - v24 mdat3<13> io ac10 gnd - ae2 gnd - af20 madd2<12> out v25 mdat3<12> io ac11 mdat2<17> io ae3 mdat1<26> io af21 madd2<9> out v26 gnd - ac12 vdd - ae4 mdat1<27> io af22 madd2<6> out w1 mdat1<7> io ac13 gnd - ae5 mdat1<28> io af23 madd2<3> out w2 mdat1<8> io ac14 mdat2<26> io ae6 mdat2<0> io af24 madd2<1> out w3 mdat1<9> io ac15 gnd - ae7 mdat2<3> io af25 madd2<0> out w4 gnd - ac16 gnd - ae8 mdat2<6> io af26 vdd - table 3.1 pin assignment (contd) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 6 3.3 pin description pin name attribute description #of pins clk clock clk is the master clock input. input 1 input signals refer to the rising edge of clk. lvttl srchn search enable srchn enables a search operation; 1 input search commences when low is lvttl signaled. inp input bus inp<39:0> is a 40-bit input bus used 40 <39:0> input search key inputs. lvttl out output bus out<17:0>, a 18-bit output bus, 18 <17:0> output outputs the associate data. lvttl oen output enable oen controls out<17:0>. oen 1 input low enables out<17:0> ; and oen lvttl high enables high-z. odonen output done odonen low active indicates that 1 output the associate data is output to the out lvttl <18:0> after a search. hon hit output hon outputs a search result. 1 output low indicates a hit; high indicates a lvttl miss hit. mle match length mle outputs match-length 6 <5:0> output information (prefix lengh-1) between lvttl the data stored in the table and the relevant search key. mloen match length output enable mloen controls mle<5:0> output 1 input enable. low enables mle<5:0>; lvttl high changes it to high-z. mdonen mle done mdonen low indicates that the 1 output completion of the search, outputting lvttl the match length to mle<5:0>. rstn reset rstn input low resets the hardware. 1 input lvttl irqn interrupt request irqn indicates low when an interrupt 1 output condition occurs in the cntl register. open drain ccmpn command execution completion ccmpn signals high during the 1 output command operation executed via cpu lvttl port, and signals low upon the completion of its execution. add cpu port address add<3:0> is a register address. 4 <3:0> input lvttl dat cpu port data bus dat<15:0> is an input/output data bus 16 <15:0> input/output for a cpu port. lvttl kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 7 pin name attribute description #of pins cen cpu port enable cen serves as the cpu port access; cen 1 input low enables the input operations of data lvttl and command. rwn read/write rwn determines the direction of the cpu 1 input bus; rwn low selects write cycle, lvttl and rwn high read cycle. fln full fln outputs low when all entries are 1 output filled with valid data. lvttl amfln almost full amfln outputs low when reaching 1 output almost full; the number of entries is lvttl equal to or exceeds the value stored in the almost full register. madd1 sram1 address madd1 is sram1 address output. 16 <15:0> output ensure that it is connected to sram1 lvttl address pins. mdat1 sram1 data bus mdat1 is a bi-directional bus for 32 <31:0> input/output sram1. ensure that it is connected to lvttl sram1 data pins. mcs1n sram1 chip enable mcs1n is sram1 chip enable signal. 1 output ensure that it is connected to sram1 lvttl chip enable. moe1n sram1 output enable moe1n is sram1 output enable signal. 1 output ensure that it is connected to sram1 lvttl output enable input. mbwe1n sram1 byte write enable mbwe1n is sram1 byte write enable 1 output signal. ensure that it is connected to lvttl sram1 byte write enable input. mbwa1n sram1 synchronous byte write enable mbwa1n is sram1 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram1 synchronous byte write enable a input. mbwb1n sram1 synchronous byte write enable mbwb1n is sram1 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram1 synchronous byte write enable b input. mbwc1n sram1 synchronous byte write enable mbwc1n is sram1 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram1 synchronous byte write enable c input. mbwd1n sram1 synchronous byte write enable mbwd1n is sram1 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram1 synchronous byte write enable d input. madd2 sram2 address madd2 is sram2 address output. 16 <15:0> output ensure that it is connected to sram2 lvttl address pins. mdat2 sram2 data bus mdat2 is a bi-directional bus for sram2. 32 <31:0> input/output ensure that it is connected to sram2 lvttl data pins. mcs2n sram2 chip enable mcs2n is sram2 chip enable signal. 1 output ensure that it is connected to sram2 lvttl chip enable. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 8 pin name attribute description #of pins moe2n sram2 output enable moe2n is sram2 output enable signal. 1 output ensure that it is connected to sram2 lvttl output enable input. mbwe2n sram2 byte write enable mbwe2n is sram2 byte write enable 1 output signal. ensure that it is connected to lvttl sram2 byte write enable input. mbwa2n sram2 synchronous byte write enable mbwa2n is sram2 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram2 synchronous byte write enable a input. mbwb2n sram2 synchronous byte write enable mbwb2n is sram2 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram2 synchronous byte write enable b input. mbwc2n sram2 synchronous byte write enable mbwc2n is sram2 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram2 synchronous byte write enable c input. mbwd2n sram2 synchronous byte write enable mbwd2n is sram2 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram2 synchronous byte write enable d input. madd3 sram3 address madd3 is sram3 address output. 16 <15:0> output ensure that it is connected to sram3 lvttl address pins. mdat3 sram3 data bus mdat3 is a bi-directional bus for sram3. 32 <31:0> input/output ensure that it is connected to sram3 lvttl data pins. mcs3n sram3 chip enable mcs3n is sram3 chip enable signal. 1 output ensure that it is connected to sram3 lvttl chip enable. moe3n sram3 output enable moe3n is sram3 output enable signal. 1 output ensure that it is connected to sram3 lvttl output enable input. mbwe3n sram3 byte write enable mbwe3n is sram3 byte write enable 1 output signal. ensure that it is connected to lvttl sram3 byte write enable input. mbwa3n sram3 synchronous byte write enable mbwa3n is sram3 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram3 synchronous byte write enable a input. mbwb3n sram3 synchronous byte write enable mbwb3n is sram3 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram3 synchronous byte write enable b input. mbwc3n sram3 synchronous byte write enable mbwc3n is sram3 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram3 synchronous byte write enable c input. mbwd3n sram3 synchronous byte write enable mbwd3n is sram3 synchronous byte write 1 output enable signal. ensure that it is connected to lvttl sram3 synchronous byte write enable d input. vdd supply the voltage required is 3.3v. 24 gnd ground ground pin. 49 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 9 4. functional descriptions 4.1 overview kl5blme064 is a search device for 40-bit ip address searches in ip routing applications. its capability extends beyond a simple lookup of data entries stored in a routing table. with its compatibility with the cidr (classless inter-domain routing), it outputs associated data for the longest match data when there are multiple matching entries. KE5BLME064 also has the search capability of finding the exact 40-bit match for searching the host address. moreover, lme064 provides a solution to routes having the same address with different prefix length. let us assume, for instance, the presence of both 0.192.1.0.0/24 and 0.192.1.0.0/32 in a routing table; the search key of 0.192.1.1.2 outputs associated data relative to 0.192.1.0.0/24 whereas the search key of 0.192.1.0.3 outputs ones relative to 0.192.1.0.0/32. kl5blme064 is a triple-port architecture equipped with task-specific ports: input port conducting a search, output port effecting a result, and cpu port executing commands and accessing to a register. this triple-port architecture facilities insertion and deletions of entries without interrupting a search operation. in order to store data, lme064 operates with 3pcs of 2mbits sram. 4.2. reset the lme064 device requires a reset after chip power up. a reset can be applied by either supplying a low pulse to the rstn pins or writing any data onto a reset register. the values reassigned for both pins and registers are as follows: registers pins cntl: 0000000b irqn: high-z stat0: 1x00b fln: high stat1: 0000000b amfln: high pr0 C rr2: unknown ccmpn: low almost full constant: 7fffh odonen: high default associate data: unknown mdonen: high entry counter constant: 0000h hon: high mcs#n: high moe#n: low kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 10 mbwe#n: high mbwa#n high mbwb#n high mbwc#n high mbwd#n high (#: 1, 2, 3) 4.3. initialization when the initialize command is executed, insertion / deletion queue and search table are initialized, entry counter constant becomes 0000h. this command is suitable for constructing a new search table. as in using other command, before proceeding with the subsequent commands, check anew by monitoring the ccmpn pin whether the initialization process has been completed. 4.4. data insertion to enter data in the table, use the insert command. ensure that the ip address is set to wr0-2, the associated data(asd) to wr3-4, and pl (prefix length C1) to wr2. example: when inserting 0.192.1.2.0/32 with associated data 3456h, enter the following. wr0: ip[15:0] 0200h (2.0) wr1: ip[31:16] c001h (192.1) wr2: 2bxx, pl[5:0], ip[39:32] 1f00h (31=32-1.0) wr3: asd[15:0] 3456h wr4: 14bx..x, asd[17:16] 0000h ensure that the value entered in wr2 is the prefix-length minus 1, not the prefix- length itself. please put the value of 0 in the host address part. the completion of the insert command is confirmed by a low signal on the ccmpn pin. proceed with the subsequent commands after checking the ccmpn status. actually, the data is acknowledged as the data of the search table within 20 clocks after the insert command is issued and the entry counter is increased before the completion of the insert command. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 11 notes: l even if the signal of the ccmpn pin becomes low level on the completion of the insert command, the inserted data is not stored in the search table and the entry counter is not increased when the search table is full (the signal of fln pin is low). l the entry counter does not increase when ip address and pl (prefix length -1) of the inserted data are the same as that of the retrieval table on the completion of the insert command. l these status are known as the value of stat1 register. lme064 is capable of storing the exact data match, i.e., the entry data hitting only when all the 40 bits coincide with the input key data. when inserting exact match data, set 39 to wr2 (pl[5:0]) because this device considers the prefix length to be a range of the retrieval. this particular function is useful for storing the host address in the table. 4.5. search to conduct a longest match search, apply data to inp [39:0], and set a srchn pin low (see fig.4.1). at the 18th clock after starting a search, mdonen will be changed to low, allowing both mle [5:0] and hon to output. mle [5:0] output should be equal to the match length minus one. that is to say, mle [5:0] is the maximum value of the match length of a search key minus 1. the hon status indicates a lookup result, with low a hit, and high as a miss hit. mdonen will revert from high to low after 4 clock cycles, while both mle [5:0] and hon will be held until the next lookup result. at the 37th clock after starting a search, odonen will be changed into low, allowing out [17:0] to output associated data. if the search results in a miss match, the value pre-registered at the default associated data will be returned and mle[5:0] output is 00h. odonen will revert from high to low after 4 clock cycles, whereas out [17:0] will be held until the next result. for instance, let us assume the presence of the following data in the table: 0.133.5.0.0/24 [associated data: 01111h] 0.133.5.16.0/32 [associated data: 02222h] cf. default associated data: 00000h kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 12 the result is as follows: search key result hon status mle[5:0] out[17:0] 0.133.5.16.2 hit at 0.133.5.16.0/ 32 low 31 (1fh) 02222h 0.133.5.17.3 hit at 0.133.5.0.0/2 4 low 23 (17h) 01111h 0.133.6.0.1 miss hit* high 0 00000h note: * indicates that0.133.5.0.0 and 0.133.6.0.1 have the matching length of 22bits; a miss hit occurs because the matching length is shorter than the registered value of 24. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 13 clk srchn inp<39:0> hon mdonen mle<5:0> odonen out<17:0> 37 clocks 4 clocks key1 key2 search result of key 1 search result of key 1 search result of key 1 search result of key 2 search result of key 2 search result of key 2 10 clocks min. 4 clocks 18 clocks 18 clocks 37 clocks fig. 4.1 search timing kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 14 4.6. data deletion to delete data from the table, use the delete command. ensure that the ip address is set to wr0-2, and pl to wr2 with a prefix-length minus 1 before executing the commands. example: if deleting 0.192.1.2.0/32, set the registers as follows. wr0: ip[15:0] 0200h (2.0) wr1: ip[31:16] c001h (192.1) wr2: 2bxx, pl[5:0], ip[39:32] 1f00h (31=32-1.0) the completion of the delete command will be confirmed by a low status of ccmpn pin. before proceeding with the subsequent commands, check anew to confirm that the delete command execution has finished. actually, the data is acknowledged as the deleted data of the search table within 20 clocks after the delete command is issued and the entry counter is decreased before the completion of the delete command. notes: l ensure that the value set to wr2 is the prefix-length minus 1, not the prefix- length itself. no deletion can be performed if the value entered to wr2 differs from that of the initial entry, that is the prefix-length minus 1, and the entry counter is not decreased. l even if the signal of the ccmpn pin becomes low level on the completion of the delete command, no deletion can be performed if the value entered to wr0-2 differs from that of the search table entry and the entry counter is not decreased. l these status are known as the value of stat1 register. 4.7. data insertion/deletion rate the maximum insertion rate is about 400k entries per second (at 66mhz system clock operation) after the initialize command is executed. this rate is performed on the condition that each new ip address data is sequentially inserted from the small one to kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 15 the large one. contrary, the minimum insertion rate is about 1.4k entries per second after the initialize command, this is on the condition that each new ip address data is inserted one by one in large the order. when both of data a and data b have the same ip data, it is preferable to insert the data with the small value of pl (prefix length C1) previously . however, this is not to required. the typical insertion/deletion rate during search operations is about 500 entries per second and worst insertion/deletion rate is about 250 entries per second. the maximum waiting time between insertion/deletion commands is about 30msec (at 66mhz system clock operation). 4.8. search via cpu port a search can be performed with the cpu port commands, independently of the input port operation. apply a search key data to wr0-2 to execute the search command. upon completion of a table lookup, associated data will be written to rr0-1; and both ml (prefix-length minus one) and hit-or-miss-hit information will be written to rr2. the command execution can be confirmed by monitoring the ccmpn pin status; before proceeding with subsequent commands, ensure that the ccmpn pin is changed to low. 4.9. interruption some statues of interrupt are defined in this device, that can be heard of by reading the stat1 register. also the generation of interrupt can be known according to the signal of irqn pin when the interrupt with irqn pin is defined in cntl register. when the stat1 register is red, the value of stat1 register should revert each bit to 0 and interrupt with irqn pin should be cleared. refer to 6.2. register description for the interrupt event with irqn pin which can concretely be defined. interruption is not accomplished unless one of the conditions is met, as described in 6.2. register description. for instance, setting both bit 2 and bit 0 of the cntl register to 1 activates the interrupt operation upon completion of either the initialize command or the table fulfillment process. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 16 notes: l the interrupt operation set to the bit 6 occurs only after the data is not deleted from search table against deletion command, because there isnt that data in search table. no other commands are valid. l the interrupt operation set to the bit 5 occurs only after a new data is stored in search table by insertion command but the entry counter is not increased, because a data as which ip address and pl (prefix length C1) are the same already exists in search table. no other commands are valid. l the interrupt operation set to the bit 4 occurs only after a new data is not stored in search table against insertion command, because search table is full. no other commands are valid. l the interrupt operation set to the bit 3 occurs only after the executions of search/insert/delete commands. no other commands are valid. l the interrupt operation set to the bit 2 occurs only after the execution of the initialize command. no other commands are valid. l the interrupt operation set to the bit 1 occurs only after the execution of either the insert or delete command when the values registered in the entry count match those of the almost full register. see the example below: example: entry count = 999 (3e7h)/almost full register = 1000 (3e8h) command entry count interruption amfln insert 1000 generated low a read stat1 1000 not generated low a insert 1001 not generated low a insert 1002 not generated low a delete 1001 not generated low a delete 1000 generated low a delete 999 not generated high kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 17 l the interrupt operation set to the bit 0 occurs only after the table becomes full. 4.10. typical operational flow (1) turn on the power. (2) reset input a low pulse to a rstn. (3) initialize. write initialize (0004h) onto the com register (00h). wait for ccmpn to turn to low. (4) set the default associate data: (a) write ffffh onto wr0 (04h). (b) write 0000h onto wr1(05h). write set default associated data (0007h) onto the com register (00h). (c) wait for the ccmpn to low. (5) data insertion 1 (a) write 0000h onto wr0 (04h). (b) write c018h onto wr1 (05h). (c) write 1c00h onto wr2 (06h). (d) write 1111h onto wr3 (07h). (e) write xxx0h onto wr4 (08h). (f) write insert (0002h) onto the com register (00h). (g) wait for ccmpn to turn to low 0.192.24.0.0/29 will be registered with associated data 01111h in a table entry counter becomes 1. (6) data insertion 2 (a) write 0800h onto the wr0 (04h). (b) write c018 onto the wr1 (05h). (c) write 1d00h onto the wr2 (06h). (d) write 2222h onto the wr3 (07h). (e) wrote xxx0h onto the wr4 (08h). (f) write insert (0002h) onto the com register (00h). kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 18 (g) wait for ccmpn to turn to low. 0.192.24.8.0 /30 will be registered with associated data 02222h in the table. entry counter becomes 2. (7) data insertion 3 (a) write 0000h onto the wr0 (04h). (a) write c018h onto the wr1 (05h). (b) write 1400h onto the wr2 (06h). (c) write 0000h onto the wr3 (07h). (d) write xxx0h onto the wr4 (08h). (e) write insert (0002h) onto the com register (00h). (f) wait for the ccmpn to turn to low. 0.192.24.0.0/21 will be registered in the table with associated data 00000h. entry counter becomes 3. (8) data lookup 1 (g) start with 0.192.24.1.2 (00c0180102h): result hit hon low mle [5:0] 1ch out [17:0] 01111h (9) data lookup 2 start with 0.192.25.1.2 (00c0190102h): result: hit hon: low mle [5:0] 14h out [17:0] 00000h (10) data lookup 3 start with 0.192.24.10.11(00c0180a0bh): result: hit kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 19 hon: low mle [5:0] 1dh out [17:0] 02222h (11) data lookup 4 start with 0.193.24.10.11 (00c1180a0bh): result: miss hit hon: high mle [5:0] 00h out [17:0] 0ffffh (12) data insertion 4 (a) write 0102h onto the wro (04h). (b) write c018h onto the wr1 (05h). (c) write 2700h onto the wr2 (06h). (d) write 1234h onto the wr3 (07h). (e) write xxx0h onto the wr4 (08h). (f) write insert (0002h) onto the com register (00h). the host address 0.192.24.1.2/40 will be stored with associated data 01234h. entry counter becomes 4. (13) data insertion 5 (a) write 0000h onto wr0 (04h). (b) write c018h onto wr1 (05h). (c) write 1c00h onto wr2 (06h). (d) write 3333h onto wr3 (07h). (e) write xxx0h onto wr4 (08h). (f) write insert (0002h) onto the com register (00h). (g) wait for ccmpn to turn to low 0.192.24.0.0/29 will be registered with associated data 03333h in a table entry counter maintains the value of 4, because there is already the data which has the same ip address and pl(prefix length - 1). (14) data lookup 5 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 20 start with 0.192.24.1.2 (00c0180102h): result: hit hon: low mle [5:0] 27h out [17:0] 01234h (15) data lookup 6 start with 0.192.24.1.3 (00c0180103h): result: hit hon: low mle [5:0] 1ch out [17:0] 03333h (16) data deletion (a) wait for the ccmpn to turn to low. (b) write 0000h onto the wr0 (04h). (c) write c018h onto the wr1 (05h). (d) write 1400h onto the wr2 (08h). (e) write delete (0003h) onto the com register (00h). 0.192.24.0.0/21 will be deleted. entry counter becomes 3. (17) data lookup 7 start with 0.192.25.1.2 (00c0190102h): result: miss hit hon: high mle [5:0] 00h out [17:0] 0ffffh 4.11. cascade connection to compose a bigger search table, two or more devices can be connected. the example is shown in figure 4.11. each device has a different search table basically, and works completely independently. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 21 when the search operates, data to which each device matches longest in the table is output. the values of mle[5:0] from each device should be compared respectively. after that, out[17:0] of the device with the largest the mle[5:0] value only has to be selected. the command of each device from cpu port is often executed respectively . therefore, the cen signal of each device should be made optional independently. figure 4.11 cascade connection output port clk srchn cen1 irqn1 fln1 amfln1 ccpmn1 odonen1 out[17:0] oen1 hon1 mdonen1 mloen1 mle[5:0] cpu port sram1,2,3 port input port add[3:0] device #1 rstn rwn dat[15:0] output port clk srchn inp[39:0] cenn irqnn flnn amflnn ccpmnn odonenn out[17:0] honn mdonenn mloenn mle[5:0] cpu port sram1,2,3 port input port add[3:0] device #n rstn rwn dat[15:0] inp[39:0] controller oenn cen1 cenn fln1 amfln1 ccpmn1 odonen1 hon1 mdonen1 flnn amflnn ccpmnn odonenn honn mdonenn kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 22 5. sram 5.1. sram specification when using KE5BLME064, ensure that the corresponding sram meets the following requirements: 2mbits flow through type synchronous burst sram (64k-word x 32bits) l voltage: 3.3v l access time: 9ns eg. micron mt58lc64k32b4 5.2. connecting to sram for the connection of lme064 to sram, see fig. 5.1 below. fig. 5.1 connection to sram sa[15:0] adsc# dq[31:0] ce2# ce# zz bwe# bwa# mode bwb# gw# bwc# adsp# bwd# adv# oe# ce2 sarm 2 sa[15:0] adsc# dq[31:0] ce2# ce# zz bwe# bwa# mode bwb# gw# bwc# adsp# bwd# adv# oe# ce2 sa[15:0] adsc# dq[31:0] ce2# ce# zz bwe# bwa# mode bwb# gw# bwc# adsp# bwd# adv# oe# ce2 sram 3 sram 2 sram 1 madd1[15:0] mdat1[31:0] mcs1n mbwe1n mbwa1n mbwb1n mbwc1n mbwd1n moe1n madd2[15:0] mdat2[31:0] mcs2n mbwe2n mbwa2n mbwb2n mbwc2n mbwd2n moe2n madd3[15:0] mdat3[31:0] mcs3n mbwe3n mbwa3n mbwb3n mbwc3n mbwd3n moe3n lme064 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 23 6. register 6.1. register map table 6.1 register address 6.2. register description com (command register) write only add [3:0] = 0h: write the 16-bit op code below in the com register for a command execution: command op code use register nop 0000h - search 0001h wr0,wr1,wr2, rr0, rr1,rr2 insert 0002h wr0, wr1, wr2, wr3, wr4 delete 0003h wr0, wr1,wr2 initialize 0004h - set almost full register 0005h wr0 set default associated data 0007h wr0, wr1 write sram 0008h wr0, wr1, wr2, wr3 read almost full register 0015h rr0 read default associated data 0017h rr0, rr1 read sram 0018h wr0 , wr1, rr0, rr1 return entry count 001bh rr0 table 6.2 op code register name address type com 0h write cntl 1h r/w stat0 2h read stat1 3h read wr0 4h write wr1 5h write wr2 6h write wr3 7h write wr4 8h write rr0 9h read rr1 ah read rr2 bh read reset fh write kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 24 cntl (control register): add [3:0] = 01h: controls the configuration of an interrupt operation with the signal of irqn pin. bit 6 1: enables interruption on the data is not deleted from search table against deletion command because there isnt that data in search table. bit 5 1: enables interruption on a new data is stored in search table by insertion command but the entry counter is not increased because a data as which ip address and pl(prefix length C1) are the same already exists in search table. bit 4 1: enables interruption on a new data is not stored in search table against insertion command because search table is full. bit 3 1: enables interruption on the completion of search/ins/del command bit 2 1: enables interruption on the completion of initialize command bit 1 1: enables interruption on table reaching almost full point bit 0 1: enables interruption on table reaching full default value 0000000b stat0 (status register): add [3:0] = 02h: this register stores four kinds of status information during operation. bit 3 1: last command complete / 0: not yet complete bit 2 1: cpu search hit / 0: cpu search miss hit bit 1 1: table almost full / 0:table not almost full bit 0 1: table full / 0:table not full default value 1x00b bit 2 is valid after the search command is executed until the next search command is engaged. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 25 stat1 (interrupt status register): add [3:0] = 03h: this register shows seven kinds of interruption information. the register will be cleared after reading is completed. irqn will be cleared when this register is read even if the interrupt status is remaining. bit 6 1: interruption on the data is not deleted from search table against deletion command because there isnt that data in searchtable. bit 5 1: interruption on a new data is stored in search table by insertion command but the entry counter is not increased because a data as which ip address and pl (prefix length C1) are the same already exists in search table. bit 4 1: interruption on a new data is not stored in search table against insertion command because search table is full. bit 3 1: interruption on the completion of search/ins/del command bit 2 1: interruption on the completion of initialize command bit 1 1: interruption on table reaching almost full point bit 0 1: interruption on table reaching full default value 0000000b wr0-4 (write register): wr0: add[3:0] = 04h wr1: add[3:0] = 05h wr2: add[3:0] = 06h wr3: add[3:0] = 07h wr4: add[3:0] = 08h stores the data required for the command executions. see table 6.2, op code for registers specific to each command. rr0-2 (read register): rr0: add[3:0] = 09h rr1: add[3:0] = 0ah rr2: add[3:0] = 0bh kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 26 the data set to rr0-rr2 is valid until the next command is engaged. rr0-rr2 has unknown values when the command with no return value to these registers is executed. reset (reset register): add [3:0] =0fh write onto this register to activate the reset command. this operation is the same as the rstn pin requiring a low pulse input. kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 27 7. command description writing the op code onto the com register (00h) enables a command execution. upon completion of the command execution, bit3 of stat0 will be changed to 1, and ccmpn to low. throughout the execution of a particular command, the execution of the other commands is prohibited; and rewriting to the wr register is also prohibited. should rewriting to either the wr register or the com register occur, the proper command execution may not be maintained. nop (op code: 0000h): no operation. search(op code: 0001h): when this command is executed, a lookup operation starts with a key value in wr0-2. upon completion of this command, associated data is written to rr0-1, and ml (match length minus 1) to rr2, setting a bit 3 (command complete) of stat0 to 1. the bit 15 of rr2(h) shows a lookup result, registering either 1 as a hit or 0 as a miss hit. wr1 wr0 15 0 15 0 ip address (31 -16 ) ip address ( 15 - 0) wr2 15 7 0 ip address (39 -32 ) rr1 rr0 1 0 15 0 associated data (17-16) associated data ( 15 - 0) rr2 15 5 0 h ml ( 5-0 ) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 28 insert (op code: 0002h): to execute this command, write the entry data (ip address) to wr0-wr2, the associated data to wr3-4, and the pl (prefix length minus 1) to wr2. the value of host address part should be all 0. the execution of this command prompts storing these data to the table. when the insertion is completed, bit3 of stat0 will be changed to 1, and ccmpn to low. wr1 wr0 15 0 15 0 ip address (31 -16 ) ip address ( 15 - 0) wr2 13 8 7 0 pl( 5-0 ) ip address (39 -32) wr4 wr3 1 0 15 0 associate data (17-16) associated data ( 15 - 0) delete (op code: 0003h): to execute this command, write the entry data (ip address) to wr0-wr2and pl (prefix length minus 1) to wr2. the value of host address part should be all 0. the execution of this command prompts deleting the data from the table. upon completion of the data deletion, bit3 of stat0 will be changed to 1, and ccpmn to low. wr1 wr0 15 0 15 0 ip address (31 -16 ) ip address ( 15 - 0) wr2 13 8 7 0 pl( 5-0 ) ip address (39 -32) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 29 initialize (op code: 0004h): when this command is executed, the insertion/deletion queue and search table will be cleared. the entry counter becomes 0000h. upon completion of the command, the cntl register, almost full register, and default associate data will maintain their current value, while stat0 will have the default. bit 3 of stat0 (command complete) will be changed to 1, as in using other command, and ccmpn to low. set almost full register (op code: 0005h): the value in wr0 is set to almost full register. upon completion of the command, bit3 of stat0 (command complete) will be changed to 1, and ccmpn is changed to low. when the number of entries is greater than or equal to the almost full register value, amfln will be changed to low with bit1of stat0 set to 1. interrupt is activated when the number of entries is equal to the almost full register value. wr0 15 0 almost full entry count ( 15-0 ) default value of almost full register is 7fffh. read almost full register (op code: 0015h): the value in almost full register is set to rr0. upon completion of the data setting to rr0, bit3 of stat0 (command complete) is changed to 1,' and ccmpn to low. rr0 15 0 almost full entry count ( 15-0 ) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 30 set default associated data (op code: 0007h): the value in wr0-1 is set as the default associated data, which is output when a miss hit occurs. upon completion of the data input to the internal register, bit3 of stat0 will be changed to 1, and ccmpn to low. wr1 wr0 1 0 15 0 default associate data (17-16) default associated data ( 15 - 0) read default associated data (op code: 0017h): the default associate data is written to rr0-1. upon completion of the data setting to rr0-1, bit3 of stat0 (command complete) will be changed to 1, and ccmpn to low. rr1 rr0 1 0 15 0 default associate data (17-16) default associate data ( 15 C 0) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 31 write sram (op code: 0008h): the data in wr2-3 is written to sram; in advance, the address of sram is specified by the value in wr0-wr1. upon the completion of the command, bit3 of stat0 will be changed to 1, and ccmpn to low. wr1 wr0 1 0 15 0 sram device id (17 C16 ) sram address ( 15 C 0) 00: reserved 01: sram1 10: sram2 11: sram3 wr2 15 0 sram data ( 15 C 0) wr3 15 0 sram data ( 31 C 16) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 32 read sram (op code: 0018h): the data of sram is read and written to rr0-1; in advance, the address of dram is specified by the value in wr0-wr1. upon completion of the command, bit3 of stat0 will be changed to 1, and ccmpn to low. wr1 wr0 1 0 15 0 sram device id (17 C16 ) sram address ( 15 C 0) 00: reserved 01: sram1 10: sram2 11: sram3 rr0 15 0 sram data( 15 C 0) rr1 15 0 sram data ( 31 C 16) return entry count (op code: 001bh): the current number of entries in the table is set to rr0. upon completion of the data setting to rr0, bit3 of stat0 will be changed to 1, and ccmpn to low. rr0 15 0 entry count ( 15-0 ) kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 33 8. package outline index d c 0.6 0.10 2.30 0.20 s 0.15 s ywvutrpnmlkjhgfedcba 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 a a a b a c a d a e a f 0.635 typ 31.75 0.20 416- 0.750 0.15 b 1.27 0.20 a 35.00 0.20sq 32.50 0.10sq unit: mm kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 34 9. electrical characteristics 9.1. absolute maximum rating item symbol condition unit note supply voltage vdd -0.3 ~ 4.0 v input voltage vi -0.3 ~ vdd+0.3 v * output voltage vo -0.3 ~ vdd+0.3 v * i/o voltage vio -0.3 ~ vdd+0.3 v * storage temperature tstg -40 ~ +125 c note : items with * indicate that input and output are not 5v tolerant. 9.2. operating conditions item symbol minimum typical maximu m unit supply voltage vdd 3.0 3.3 3.6 v ambient operating temperature ta 0 +25 +70 c 9.3. dc characteristics item symbo l minimum typical maximu m unit condition input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 8ma output high voltage voh 2.4 v ioh = -8ma input leakage current iil -10 m a vin = gnd kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 35 output leakage current iih 10 m a vin= -vdd output leakage current ioz -10 10 m a high impedance standby current idds tbd m a dynamic operating current iddop tbd ma 9.4. ac characteristics ta = 0~70c, vdd = 3.3v 0.3v input /output port no. parameter min. max. unit 1 clock cycle time 15 100 ns 2 clk high time 5 ns 3 clk low time 5 ns 4 inp setup time to clk high 4 ns 5 clk high to inp hold time 1 ns 6 srchn setup time to clk high 4 ns 7 clk high to srchn hold time 1 ns 8 clk high to out valid 1 15 ns 9 oen low to out active 1 ns 10 oen high to out high-z 10 ns 11 clk high to odonen low 1 15 ns 12 clk high to odonen high 1 15 ns 13 clk high to mle valid 1 15 ns 14 mloen low to mle active 1 ns 15 mloen high to mle high-z 10 ns 16 clk high to mdonen low 1 15 ns 17 clk high to mdonen high 1 15 ns 18 clk high to hon valid 1 15 ns kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 36 cpu port no. parameter min. max. unit 19 add setup time to cen low 8 ns 20 cen high to add hold time 3 ns 21 dat setup time to cen high 8 ns 22 cen high to dat hold time ( write ) 3 ns 23 rwn setup time to cen low 8 ns 24 cen high to rwn hold time 3 ns 25 cen low to dat active 22 ns 26 cen low to dat valid 25 ns 27 cen high to dat hold time ( read ) 1 ns 28 cen high to ccmpn high 25 ns 29 clk high to ccmpn low 25 ns 30 clk high to fln valid 25 ns 31 clk high to amfln valid 25 ns 32 clk high to irqn low 25 ns 33 cen low to irqn high-z 4 clks +15 ns 34 cen cycle time 45 ns 35 cen high time 15 ns 36 cen low time 30 ns 37 rstn low pulse width 60 ns 38 rstn low to hon high 45 ns 39 rstn low to fln high 45 ns 40 rstn low to amfln high 45 ns 41 rstn low to ccmpn low 45 ns 42 rstn low to irqn high-z 45 ns 43 rstn low to odonen high 45 ns 44 rstn low to mdonen high 45 ns 45 cen low to hon high (reset reg. ) 45 ns 46 cen low to fln high (reset reg. ) 45 ns 47 cen low to amfln high (reset reg. ) 45 ns 48 cen low to ccmpn low (reset reg. ) 45 ns 49 cen low to irqn high-z (reset reg. ) 45 ns 50 cen low to odonen high (reset reg.) 45 ns 51 cen low to mdonen high (reset reg. ) 45 ns sram port no. parameter min. max. unit 52* clk high to sram control signal valid 11 ns 53* clk high to sram control signal hold time 2 ns 54* sram data setup time to clk high 4 ns 55* clk high to sram data hold time 0.5 ns kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 37 misc no. parameter unit 56 srchn low to srchn low 10n or 40+m n=1,2,3,4 m=1,2,3,.... cycles note: characteristics are measured under the following conditions. *: in case of no.52, 53, 54, 55 of ac caracteristics input "h" level input "l" level input reference voltage input signal through rate output judgment level logical capacitance(cl) "h" level output loading current(ioh) "l" level output loading current(iol) dut cl ioh vdd/2 iol test loads 3.3v 0.0v 1.5v 1.0ns/v vdd/2 50pf(20pf*) -8ma 8ma kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 38 fig. 9.1 input port timing 1 2 3 4 5 6 7 clk inp<39:0> srchn kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 39 fig.9.2 output port timing (1) 9 clk out<17:0> valid odonen out<17:0> oen 11 12 8 10 4 clocks kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 40 fig. 9.3 output port timing (2) clk mle<5:0> valid mdonen hon 4 clocks 16 17 13 18 mle<5:0> mloen 14 15 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 41 fig.9.4 search timing clk srchn inp<39:0> hon mdonen mle<5:0> odonen out<17:0> 37 clocks 18 clocks 4 clocks 4 clocks 18 16 17 13 11 12 8 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 42 fig. 9.5 cpu port write timing cen 35 36 34 add<3:0> dat<15:0> rwn 20 19 21 22 23 24 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 43 fig. 9.6 cpu port read timing cen add<3:0> dat<15:0> rwn 20 19 25 27 23 24 35 36 34 26 valid kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 44 fig. 9.7 cpu port timing (1) clk ccmpn cen 29 28 fln amfln 30 31 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 45 fig. 9.8 cpu port timing (2) clk cen irqn 32 33 irqn kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 46 fig. 9.9 reset timing via rstn pin rstn hon fln amfln ccmpn irqn odonen mdonen 37 38 39 40 41 42 43 44 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 47 fig. 9.10 reset timing via reset register cen hon fln amfln ccmpn irqn odonen mdonen 45 46 47 48 49 50 51 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 48 fig. 9.11 sram read timing clk madd#[15:0] 52 53 valid mbwe#n, mbwa#n - mbwd#n mcs#n moe#n 53 mdat#[31:0] valid 54 55 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 49 fig. 9.12 sram write timing clk madd#[15:0] 52 53 valid mbwe#n, mbwa#n - mbwd#n mcs#n 53 moe#n 53 mdat#[31:0] valid 52 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 50 fig. 9.13 minimum search period clk srchn 56 kawasaki lsi 64k longest match search engine (KE5BLME064) preliminary version 2.5.4 proprietary and confidential 51 kawasaki lsi reserves the right to make changes without further notice to any products herein to improve reliability, function or design. kawasaki lsi does not assume any responsibility or liability arising out of the application, use of any product, or circuit described herein; nor does it convey any license under its patent rights, copyrights, trademark rights, or any other of the intellectual property rights of kawasaki lsi or of third parties.. kawasaki lsi products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body or any other applications intended to support or sustain life; nor are they for any other applications where the failure of the kawasaki lsi products for any such unintended or unauthorized application may create a situation where personal injury or death may occur. the buyer shall indemnify and hold kawasaki lsi and its officers, employees subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that kawasaki lsi was negligent regarding the design or manufacture of the parts. for more information or questions regarding kawasaki lsi products, contact the addresses below: kawasaki lsi u.s.a. inc. 2570 north first street, suite #301 san jose, ca 95131 tel. (408) 570-05555 fax (408) 570-0567 e-mail: info@klsi.com 501 edgewater dr., suite 510 wakefield, ma 01880 tel. (617) 224-4201 fax (617) 224-2503 kawasaki steel corporation makuhari techno-garden b5 1-3 nakase minami-ku, chiba 261-01 japan tel. (81)-43-296-7432 fax (81)-43-296-7419 |
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